1. Field of the Invention
The present invention relates to a semiconductor device having a via hole (a through hole) which is formed penetrating through a semiconductor substrate so as to be electrically connected to a reverse of the substrate, or a semiconductor device having a plated heat sink (abbreviated to xe2x80x9cPHSxe2x80x9d) layer for heat radiation and stress alleviation at a reverse of the semiconductor substrate.
2. Description of the Related Art
In an analog integrated circuit of a high frequency or a high output amplifying device made of a field-effect transistor (FET), a hetero-bipolar transistor (HBT) or the like, there are formed a via hole (a through hole) penetrating a substrate and a penetrating metal of an electric conductor inside of the via hole in order to ground from a circuit device formed on the semiconductor chip with a low impedance, and thus, they are electrically connected to a back electrode disposed over the entire reverse of the semiconductor chip, thereby achieving the grounding.
In this case, although a metal wire may be used for the purpose of the grounding, the wiring becomes long, so that an inductance component or a resistance component is increased, resulting in abnormal oscillation in an unstable state.
In view of this, the semiconductor chip is connected directly to the back electrode through the substrate at a short distance for the purpose of the grounding, thereby suppressing the component of the inductance or resistance to a low level. Thereafter, the semiconductor chip is securely bonded at the metallic reverse thereof to a metallic surface of a package substrate, a package or the like with a metallic soldering material (a solder), thus ensuring the grounding.
In the meantime, a wiring pad provided on the semiconductor chip and a terminal of the package substrate, the package are connected to each other by bonding via a metal wire.
The structure of a semiconductor apparatus having such via hole is disclosed in, for example, Japanese Unexamined Patent Publication (KOKAI) Nos. 59-117171, 61-79261 and 5-47937.
FIG. 7 is a cross-sectional view schematically showing the structure of a semiconductor apparatus (a semiconductor chip) shown in the prior art; and FIG. 8 is a cross-sectional view illustrating the state in which the semiconductor chip in the prior art, shown in FIG. 7, is bonded to a package metal mount such as a package with a soldering material.
In the semiconductor chip shown in FIG. 7, a semiconductor device of a field-effect transistor (FET) is disposed at the obverse of a semiconductor substrate 1 made of semi-insulating GaAs.
That is to say, a device region formed of an n-type GaAs conductive layer 2 is disposed at the obverse of the semiconductor substrate 1 made of semi-insulating GaAs. Furthermore, on the GaAs conductive layer 2 are formed a Schottky gate electrode 5, and a source electrode 3 and a drain electrode 4 which sandwich the gate electrode 5 therebetween. The semiconductor device is covered with an insulating film 7 made of SiO2 or the like.
Moreover, a through a hole (i.e., via hole) 6 penetrating the semiconductor substrate 1 from the obverse thereof down to the reverse thereof is formed near the source electrode 3. As penetrating metals for connecting so as to ground the source electrode 3 to the reverse are laminated a titanium (Ti) layer 9, a gold (Au) layer 10 and an Au-plating layer 12 on the inner wall of the via hole 6.
On the other hand, a Ti layer 30, an Au layer 31 and an Au-plating layer 32 are laminated in this order in contact with the penetrating metals of the via hole 6 as a back electrode also over the entire reverse of the semiconductor substrate 1.
FIG. 8 illustrates an example of the arrangement in which the Au-plating layer 32 at the reverse of the semiconductor chip shown in FIG. 7 is bonded onto a metal mount having a package, a lead frame, a package substrate with a soldering material 18 made of gold tin (AuSn) or the like. The metal mount is made of copper (Cu) plated with Au.
Here, the source electrode 3 is connected to the back electrode via the penetrating metal of the via hole 6, and further, the back electrode is connected to a metal mount 19 via the conductive soldering material 18. Consequently, the source electrode 3 is grounded to the earth.
Each of the Ti layers 9 and 30 used herein is formed so as to enhance a contact property since Au is poor in contact property with respect to the semiconductor substrate. In addition, each of the Ti layers 9 and 30 is formed as thinly as, for example, in about 100 nm so as not to increase resistance.
In other words, the Ti layers in the above-described prior art never have the function of a barrier layer, which is used according to the present invention, described later.
In the meantime, the Au layer 31 laminated on the Ti layer 30 is formed as a power supplying layer for applying Au plating in the thickness of about 100 to 500 nm. The Ti layer and the Au layer are formed by sputtering vapor deposition or electron gun vapor deposition.
The wiring at the obverse and the Au-plating layer 32 of the penetrating metal are formed in the thickness of about 0.5 xcexcm to 30 xcexcm. Only the Au layer 31 formed by the vapor deposition can secure conductivity without using Au-plating layer 32.
Additionally, the thickness of the Au layer 31 or the Au-plating layer 32 in the back electrode approximately ranges from 0.5 xcexcm to 30 xcexcm. Since a device of low power consumption for low noise amplification or the like is enough to merely secure the close contact with the soldering material, the Au layer 31 or the Au-plating layer 32 is formed in the thickness of about 0.5 xcexcm by the sputtering vapor deposition or the like without applying any Au plating.
In contrast, the Au-plating layer 32 is thickly formed in a device of high power consumption for high output amplification.
Otherwise, in the above-described prior art, it is necessary to thin the semiconductor substrate in order to enhance a heat radiating property in a semiconductor device of large heat generation. Therefore, it is general to dispose a heat sink layer having a heat radiating function at the reverse of the semiconductor substrate in order to reinforce the physical strength of a chip or alleviate a stress in the case in which a stress occurs between the semiconductor substrate and the metal mount or the soldering material caused by expansion of the semiconductor substrate. Such a heat sink layer is called also a PHS (plated heat sink) layer.
In general, although gold (Au), which is soft and excellent in heat conductivity and electric conductivity, has been mostly used as such a heat sink layer, copper (Cu), which is inexpensive, soft and excellent in heat conductivity and electric conductivity, has been used in recent years.
In the prior art, gold tin (Auxe2x80x94Sn) composed of gold added with about 20% of tin has been mostly used as the soldering material for fixing the semiconductor chip to the metal mount in the case where the heat sink layer requires the reliability, and the melting point of the soldering material for fixing the semiconductor chip is set to as high as 300xc2x0 C. to 400xc2x0 C. since there are heating works thereafter such as heating in bonding, cap sealing for the package, formation of a mold resin or soldering of the package to a circuit board. As the soldering material may be used a lead tin (Pbxe2x80x94Sn) or zinc tin (Znxe2x80x94Sn) based soldering material.
Subsequently, explanation will be made on a method for fabricating the semiconductor chip having the via hole and the PHS layer.
FIGS. 9 to 15 are schematically cross-sectional views showing, in sequence, one example of a method for fabricating the semiconductor apparatus in the prior art.
First of all, as shown in FIG. 9, the n-type conductive layer 2 is epitaxially grown on the semi-insulating GaAs substrate 1 having the thickness of about 600 xcexcm. A region except for the device is removed by etching or the like, thereby forming the n-type conductive layer 2 serving as the device region. On the n-type conductive layer 2 are formed the Schottky gate electrode 5, and the source electrode 3 and the drain electrode 4, which are ohmic.
Furthermore, the semiconductor device is covered by accumulating the insulating film 7 made of SiO2 or the like serving as a protective film.
Moreover, a photoresist film 8 having an opening pattern is formed on the insulating film 7. Thereafter, the via hole 6 is formed, for example, having a diameter of about 40 xcexcm and a depth of 100 xcexcm on the GaAs substrate 1 by dry etching with gaseous chloride.
After the etching, as shown in FIG. 10, the photoresist film 8 formed at the obverse is removed, and further, the side of the insulating film 7 is etched in about 10 xcexcm, thereby exposing a part of the source electrode 3. On the exposed source electrode 3, the Ti layer 9 having the thickness of 100 nm and the Au layer 10 having the thickness of 400 nm are formed in sequence by sputtering vapor deposition. The Au layer 10 is a power supplying layer for plating, and the Ti layer 9 is a layer for bringing Au layer 10 into close contact.
Next, as shown in FIG. 11, another photoresist film 11 opened continuously to the via hole 6 and a part of the source electrode 3 is formed as a mask, and further, the Au plating layer 12 as the wiring is formed in the thickness of 3 xcexcm. Thereafter, the photoresist film 11 used as the mask for the plating is removed.
Subsequently, the Au layer 10 and the Ti layer 9 except for the wiring are removed by ion milling or the like while using the Au plating layer 12 per se as a mask.
And then, after the semiconductor device and the wiring are formed on the GaAs substrate 1, the obverse of the GaAs substrate 1 is stuck to a support plate 14 made of quartz or the like via a wax 13. Thereafter, the reverse of the GaAs substrate 1 is polished, so that the GaAs substrate 1 is thinned down to 100 xcexcm, thereby exposing the metal at the bottom inside of the via hole 6. Variations in thickness of the substrate by polishing are measured by detecting positional variations of a support rod for pressing the substrate against the polished surface.
Subsequently, as shown in FIG. 13, a Ti layer 15 in the thickness of 100 nm and an Au layer 16 in the thickness of 400 nm as a back electrode are vapor-deposited by sputtering at the reverse of the GaAs substrate 1. Incidentally, in the case of the semiconductor device of low power consumption for low noise, the semiconductor device may be cut out into semiconductor chips in this state by dicing or the like.
Next, as shown in FIG. 14, a thick photoresist film serving as a mask is formed on the reverse of the GaAs substrate 1 and in a chip cutting region, and then, the Au layer 16 as a power supplying layer is subjected to Au plating in the thickness of 20 xcexcm, thereby forming a PHS layer 23.
Subsequently, as shown in FIG. 15, the Au layer 16 and the Ti layer 15 in the cutting region are removed by ion milling or the like while using the PHS layer 23 as a mask, and further, the GaAs substrate 1 is chipped by dry etching or wet etching, or chipped by dicing.
Thereafter, the reverse is stuck to an adhesive tape, to be separated from the support plate 14 by dissolving the wax 13. The adhesive tape is laterally extended by heat, so that the interval between the chips is enlarged so as to obtain semiconductor chips one by one, thus providing the semiconductor chip (i.e., the semiconductor apparatus) shown in FIG. 7.
In the meantime, FIGS. 16 and 17 illustrate one specific example of a method for fabricating a heat sink layer 21 on the reverse of the substrate in the semiconductor apparatus in the prior art. A mask made of a thick photoresist film 20 is formed on the reverse of the substrate in the semiconductor device, which is formed in reference to FIG. 12, in the chip cutting region, as shown in FIG. 16, thereby forming the heat sink layer 21.
Thereafter, as shown in FIG. 17, the GaAs substrate 1 in the cutting region is chipped by dry etching or wet etching or chipped by dicing while using the PHS layer 21 as the mask.
In Japanese Unexamined Patent Publication (KOKAI) No. 61-79261, a Ti contact layer having a thickness of 100 nm is provided.
Alternatively, Japanese Unexamined Patent Publication (KOKAI) No. 7-193214 discloses the use of Ti, Cr or Ni having the thickness of 50 nm or less as a contact layer. Otherwise, Japanese Unexamined Patent Publication (KOKAI) No. 7-58132 discloses the use of a Ti layer having the thickness of 50 nm, and Japanese Unexamined Patent Publication (KOKAI) No. 7-176760 also discloses the use of a Ti layer having the thickness of 50 nm as a contact layer.
In this way, since Au per se is poor in contact property with respect to the substrate, a metal such as Ti is thinly formed in the thickness of 100 nm or less, thereby securing the contact property.
When the above-described semiconductor chip is boned to the metal surface of the package or the like with the soldering material which is heated and fused, in particular, the Au layer of the back electrode is thin, Sn or the like contained in the soldering material is diffused in the Au layer or the Ti layer, and further, is diffused and is impregnated into the via hole. When the heating is stopped and the temperature returns to room temperature, a crack occurs from the via hole, thereby arising a problem of breakage or deterioration of the semiconductor device or the circuit wiring having the crack at the surface thereof.
This is because Sn is excellent in wettability with respect to the metal, and therefore, Sn is diffused in the metal to readily produce an alloy. The alloyed metal is generally liable to be easily hardened.
In view of these, it is construed that the soldering material impregnated in the via hole is hardened by alloying, and thus, the crack occurs on the semiconductor substrate.
The resistance is increased in the alloyed portion, thereby reducing a drain current or degrading the device characteristics.
Additionally, also in the case in which the heat sink layer is formed on the reverse in the above-described semiconductor apparatus in the prior art, the soldering material is impregnated into the member constituting the heat sink layer, which is then hardened or denatured, resulting in lack of flexibility. Thus, there arises a problem that a distortion alleviating function is lost or heat conductivity is deteriorated to degrade a heat radiation effect.
In addition, Japanese Unexamined Patent Publication (KOKAI) No. 2-214127 discloses the technique of covering to enclose a dicing region with a heat radiating electrode disposed at the reverse of a substrate for the purpose of prevention of generation of an edge in dicing the substrate; and Japanese Unexamined Patent Publication (KOKAI) No. 2-148739 discloses the technique of removing an undercoating layer for a heat radiating electrode so as to expose a dicing region of a substrate after the formation of a heat radiating electrode for the purpose of accurate dicing in dicing by etching. Neither of the above-described prior art discloses the technique of disposing a barrier layer for preventing any diffusion of the plating component in the plating process.
Moreover, Japanese Unexamined Patent Publication (KOKAI) No. 7-193122 discloses the technique of dry-etching a device separating region for the purpose of preventing any generation of gaps or bubbles inside of a sticking member in sticking a semiconductor apparatus onto a support mount made of glass or the like, but does not disclose the technique of disposing a barrier layer for preventing any diffusion of the plating component in the plating process.
The present invention has been accomplished in an attempt to solve the above problems and overcome the drawbacks experienced in the prior art. It is an object of the present invention to provide a semiconductor apparatus having a via hole capable of excellently keeping the characteristics of a semiconductor device formed on an obverse of a semiconductor substrate without any occurrence of breakage such as a crack on the semiconductor substrate, or a semiconductor apparatus in which the reliability of a back electrode member including a heat sink layer cannot be degraded.
In order to achieve the above-described object, the present invention adopts technical arrangements described below.
Namely, a first aspect of the present invention is a semiconductor apparatus comprising: a semiconductor substrate; a first surface of the semiconductor substrate on which a semiconductor device is formed; a second surface opposite to the first surface of the semiconductor substrate; a via hole penetrating through the semiconductor substrate from the first surface to second surface; an electrode, provided on the second surface, connecting to the via hole; wherein the electrode having a barrier layer for preventing any diffusion of a soldering material into the via hole.
In a second aspect of the present invention, the electrode comprises a plurality of conductive metal layers.
In a third aspect of the present invention, the electrode comprises a metal junction layer which enhances a solder wettability of the barrier layer.
comprises electrode comprises a Ti film layer formed on the second surface of the semiconductor substrate, the barrier layer formed on the Ti film layer and a metal junction layer for enhancing a solder wettability of the barrier layer.
In a fifth aspect of the present invention, the barrier layer is composed of at least one selected from the group consisting of vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), silicides thereof and nitrides thereof.
In a six aspect of the present invention, the metal junction layer is bonded to a package of a semiconductor apparatus a via solder layer.
A seventh aspect of the present invention is a semiconductor apparatus comprising: a semiconductor substrate; a first surface of the semiconductor substrate on which an FET is formed; a second surface opposite to the first surface of the semiconductor substrate; a via hole penetrating through the semiconductor substrate from the first surface to second surface and connecting to a source electrode of the FET; an electrode, provided on the second surface, connecting to the via hole; wherein the electrode having a barrier layer for preventing any diffusion of a soldering material into the via hole.
An eighth aspect of the present invention is a semiconductor apparatus comprising: a semiconductor substrate; a first surface of the semiconductor substrate on which a semiconductor device is formed; a second surface opposite to the first surface of the semiconductor substrate; a plated heat sink provided on the second surface; a barrier layer, provided on a surface of the plated heat sink, for preventing any diffusion of a soldering material into the plated heat sink.
In the semiconductor apparatus (the semiconductor chip) according to the present invention, the metal junction layer conformable to the soldering material and the barrier layer capable of inhibiting any diffusion of the soldering material are formed on the back electrode, thus providing the stable semiconductor apparatus in which no breakage such as a crack occurs from the via hole on the semiconductor substrate, and therefore, no influence is exerted on the semiconductor device formed on the obverse of the semiconductor substrate.